In the production of a semiconductor integrated circuit, a desired circuit is formed by repeating the steps of exposing, etching, depositing (plating), and polishing of a wafer to build a laminated structure. While doing this, productivity is increased by forming a plurality of semiconductor integrated circuits simultaneously on a wafer.
In particular, in recent years, a wafer diameter is increased to increase the number of circuits that can be produced at once. However, as a wafer becomes larger, it is increasingly difficult to process a wafer evenly at the central portion and peripheral portion thereof. Moreover, miniaturization of circuits is under way and highly accurate processing may be required.
For example, in copper wiring, which is widely used nowadays, ECP (Electro-Chemical Plating), in which wiring grooves are made on an insulator and then copper plating is performed on that insulator to fill in the grooves with copper, is performed. In this process, since not only the wiring grooves but also a whole surface of the insulator are copper-plated, CMP (Chemical Mechanical Polishing) is used for polishing to expose a wiring pattern.
If large height differences are created on a wafer as a result of this CMP, the height of a copper wiring line may vary, or a short circuit of wiring caused by copper that is left unpolished may occur. In either case, the performance of a semiconductor integrated circuit may degrade, or the yield rate may be decreased.
Also, in some cases, a problem does not occur with a single layer of a circuit but occurs when another layer is laminated. This kind of problem tends to occur at a portion where the height of a lower layer is smaller than that of the surrounding area and the height of an upper layer is larger than that of the surrounding area.
To date, production of a circuit is performed and, if an error occurs, the layout of the circuit is then modified. This is very inefficient in terms of cost and time, because a wafer is first made and then modified. Thus a method which simulates CMP and performs prediction and modification prior to production is proposed (see, for example, Japanese Laid-open Patent Publication No. 2003-224098).
However, if a chip is made and modification is then performed, production cost and time are increased. Also, because chips are produced without eliminating a problematic portion, the yield rate may drop by about 10%.
When a CMP simulation is used, production cost is reduced to some extent because trial production does not need to be performed. However, a CMP simulation may take a few hours or a day to complete depending on, for example, the size of the chip to be produced. To correct a problematic portion, a CMP simulation needs to be performed several times, possibly causing the total simulation time to be a few days or weeks.
That is to say, in the known art, there is a problem in that it is time-consuming to obtain a result of CMP, and a lot of time is thus needed to determine an optimum circuit layout.
The present invention has been achieved to address and overcome the above-mentioned problem of the known art, and an object of the present invention is to provide a polish prediction and evaluation apparatus, method, and program that can predict and evaluate a result of a polishing process in a short time, thereby enhancing the speed of layout modification to increase the yield rate in a short time.